This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to improve the capacitance of metal insulator metal capacitors in semiconductor devices.
In many applications in integrated circuits, high performance, high speed capacitors are required. A metal insulator metal (MIM) capacitor is one commonly used capacitor in high performance applications in semiconductor technologies. An MIM capacitor has a sandwich structure wherein capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both of the two parallel metal plates are conventionally made from copper, aluminum or their alloys. These metals are patterned and etched needing several photolithography masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD) or other deposition processes.
The dimensions of modern integrated circuitry in semiconductor chips continues to become smaller, it can become more difficult to design a capacitor having the necessary capacitance in these smaller structures due to the limited insulator and electrode contact area. As the needed devices for a given chip design compete for the available chip area, it can be desirable to increase the capacitance of the capacitor while minimizing the horizontal footprint area devoted to the capacitor.
The present disclosure presents an advanced MIM capacitor design to alleviate this problem.